In browsing on Simgui's website, the following technical terms may be helpful to you.

Term Definition
Acceptor An impurity in a semiconductor that accepts electrons excited from the valence band.
AOG Axial Oxygen Gradient: Profile of oxygen concentration along the length of a crystal.
ASTM American Society of Testing and Materials. Known for writing standards for the industry.
Autodoping Dopant incorporated during the growth of an epitaxial layer from sources other than the dopant intentionally added to the vapor phase. Sources can include the back and front surfaces and edges of the substrate, and other substrates in the deposition assembly.
Backside Of a semiconductor or wafer; the side opposite the front or polished side of a wafer.
Backside OSF Mechanical damage on the backside of the wafer that can precipitate stacking fault defects for gettering of impurities.
BDD Bulk Defect Density
Blade Dressing Reducing the loading of the diamond blade by cleaning the silicon chips off.
Block A ground and cut section of ingot.
BMD Bulk Micro Defect
Bonded Wafer Two wafers bonded together: see SOI
Bow A measure of the convex curvature of a wafer, not desirable.
BOX Buried Oxide layer on SOI wafer
BSD Backside Damage: a process of mechanically damaging the backside of a wafer to increase gettering.
Bulk Precipitation Defects in silicon used for gettering of impurities and can include dislocation loops, stacking fault defects, and oxygen precipitate defects.
Buried Layer A diffused region that is covered with an epitaxial layer, subdiffused layer, or a diffusion under film.
C of C Certificate of Compliance: a form sent to customers indicating that the parameters specified by the customer have been met.
Cleavage Plane A break along crystal planes determined by crystal structure and always parallel to such a plane.
CMP Chemical-Mechical Polish: a process of removing surface material using chemical and mechanical means to achieve a mirror-like surface in preparation for subsequent processing.
Collimated Light Light source in which the rays are parallel. Used for surface inspection of wafers
Conductivity A measure of the ease with which electrical carriers flow in a material: the reciprocal of Resistivity.
Conductivity Type Defines the nature of the majority of carriers in the material: either N-type or P-type
COP Crystal Originated Pits
Crucible A thick-walled, white bowl-like container, usually made of quartz, in which a collection of material, such as polysilicon, is melted within a crystal puller.
Crystallographic Orientation There are three orientation planes in the silicon crystal: <100>, <110>, and <111>. (Include a diagram.) The orientation of the wafer is classified by which orientation plane the surface of the wafer is parallel to. The surface might not be exactly parallel, but slightly different, and the difference is called the displacement angle or off angle orientation. The relationship between the crystal's orientation and the radius is marked by either a notch or a flat cut into the wafer.
CVD Chemical vapour deposition
CW Chemical or Cut Wafer, a department responsible for separating the ingot sections into wafers and preparing those wafers for polishing.
CZ The Czochralski method of growing single-crystal silicon ingots.
Defect Free Region The linear distance from the frontside wafer surface to the depth of the first bulk defect.
Diffusion A method of doping or modifying the characteristics of semiconductor material by 'baking' wafers of the base semiconductor material in furnaces with controlled atmospheres of impurity materials.
Diffusion Length The distance a front side free-electron or hole can travel through a crystal. This is proportional to the Lifetime of the crystal.
Dislocation Defects in silicon ingots
DNZ Depth The linear distance from the frontside wafer surface to the depth where the defect density appears nearly uniform.
Doping or Dopant Chemical impurities added to polysilicon which will yield either n- or p-type silicon, depending on the specific dopant used.
Edge Crown The difference between the surface elevation 1/8' (3.2mm) from the edge of the slice and the elevation of the slice edges exposed in mils or microns (associated with epi layer deposition).
Edge Rounding Slices whose edges have been shaped by grinding or etching.
Epi Epitaxial (or epitaxy) process, depositing a thin layer of silicon atoms onto a wafer by condensing a controlled amount of silicon gas (silane) onto the polished surface of the wafer in a temperature-controlled environment.
Epitaxial Layer The layer or layers of semiconductor material having the same crystalline orientation as the host substrate on which it is grown.
EPW Epi Wafer
Etch To remove or dissolve surface contamination, work-damaged material (polishing), and to control thickness by chemical action with strong acid and alkaline compounds.
Etch - Mirror Used to create a clean, shiny finish for visual inspection and resistivity measurements. Also produces a good seal for annealing.
Etch - Preferential An etch that exhibits an accelerated etch rate along specific crystallographic planes.
Flatness The maximum deviation of the wafer surface from a flat plane. Flatness measurement is usually done with the backside held to a flat surface (a vacuum chuck) and excludes linear thickness variations.
Focal Plane That plane whose normal provides the shortest distance between the absolute maximum and absolute minimum on the wafer surface.
Focal Plane Deviation (FPD) Maximum deviation of the wafer surface above and below the focal plane.
FTIR Fourier Transform Infrared: a means of testing for oxygen or carbon levels in the crystal.
Gettering Gettering is a process that attracts contaminents and traps defects when the wafers are heated. Can be initiated through mechanical damage or interstial oxygen. Extrinsic gettering is caused by BSD. Intrinsic gettering is caused by interstial oxygen.
GFA Gas Fusion Analysis: a means of testing oxygen or carbon levels in the crystal.
GOI Gate Oxide Integrity
Haze Light scattering caused by microscopic surface irregularities (such as a high concentration of pits, mounds, small ridges, particles, etc.) on epitaxial wafers or polished slices. Kasumi is Japanese for mist or cloud.
ICP-AES Inductively Coupled Plasma Atomatic Emission Spectroscopy
Ingot A semiconductor grown cylinder, polysiliconcrystalline or single crystal, generally of irregular diameter or in the as-grown state.
Kerf The notch left by a saw cut. The width of a saw cut.
Kerf Loss The amount of material lost while slicing wafers. The kerf in the cut and swarf is the chips and fillings from the kerf.
Laser Mark An identification number inscribed on a wafer using a laser. The mark is customer specific.
Lifetime The average time a free-electron or hole can exist in a crystal, measured in seconds. Lifetime may vary within a crystal: bulk lifetime withing the crystal and surface lifetime at, of course, the surface.
Line Defects See Stacking Faults
Linear Thickness Variation Thickness variation within a slice whose front and back surfaces can be represented by two, nonparallel planes.
LPCVD Low Pressure CVD: deposits a layer of polysilicon to the wafer, later removed by polishing. A backside layer can act as a gettering agent.
LPD Light Particle Defect, sometimes known as particles.
Melt The pure, molten silicon from which single crystal silicon is grown in a crystal pulling furnace during the Czochralski process.
Micron A unit of length, 1/1,000,000 (one millionth) of a meter.
Nanotopology Surface variations over a small area
N-Type Material that has free-electronics created with the proper dopant.
Oi Interstitial Oxygen
OPP Optical Precipitate Profiler
OSF Oxidation Stacking Faults
P- Typically P-type material with a resistance greater than 1
P+ Typically P-type material with a resistance less than 1
P++ P-type material highly doped with boron with a resistivity between 0.005 and 0.010
Polished Surface or Side The surface of a semiconductor slice that has received extensive chemical/mechanical operations to result in a mirror-like finish. This surface will then become the basis for subsequent device fabrication. Also called the Front Side.
Polysilicon More fully known as polycrystalline silicon, a ultra pure form of silicon composed of many crystals. This is the starting material for wafer manufacture.
PP Box Poly Propylene Box: the box used to store and ship polished wafers.
P-Type Material that has free-holes created by the proper dopant.
PW Polished Wafer. Also refers to the wafer process from polishing through final inspection.
Resistivity This is a complex relation of dopants, resistivity, and conductivity. It should be noted that resistivity can vary within a wafer, both in locations and directions. The resistivity can be different in the radial and axial directions in the wafer.
ROG Radial Oxygen Gradient. Change in the concentration from the center of a crystal to the edge.
RRG Radial Resistivity Gradient. The difference between the resistivity at the center of a semiconductor slice and the value at a point, or at several symmetrically located points, away from the center of the slice, typically at half the slice radius or near the slice edge. This difference is expressed as a percentage of the center value.
Seed Crystal The seed is the starting point for growing the ingot. It must have the same crystal orientation as desired for the resulting ingot. The are made from out-of-spec p-type ingots.
SEMI Semiconductor Equipment and Materials Institute. Sets specifications for the semiconductor industry.
Shotholes Pits caused by BSD.
Slip Can occur in both PW and EPW. A process of plastic deformation in which one part of the crystal undergoes a shear displacement relative to another in a fashion that preserves the crystallinity of the material. The direction is on a specific crystallographic plan.
SOI Silicon on Insulator. Usually achieved by bonding two wafers, one of which has oxide on top..
SOQ Silicon on Quartz
SRP The resistance measured between the conductive metal of a point probe and a large area, relatively low-resistance semiconductor contact, dominated by the resistivity of the semiconductor volume close to the problem. Spreading resistance find widespread usage in the characteristization of microresistivity variations and analysis of complex device structures.
Stacking Faults A deviation from the normal stacking sequence of atoms in a crystal. How the fault appears depends on the orientation of the crystal. Normally occurs in Epi process, but also can occur in PW, where it's called OSF
Substrate Basic surface on which a material adheres. A single-crystal slice that is the basis for subsequent processing operations, such as epi layer deposition, diffusion, ion implants, etc.
Swirl Shallow pits looked for during visual inspection. Helical or concentric features that are visible to the unaided eye after preferential etch, and appear to be discontinuous under 150x magnification.
Taper A measure of the flatness of a wafer, taper being thicker at the edges than at the center
TIR Total Indicator Reading. The distance between the highest and lowest point on the wafer surface measured normal to the focal plane.
TTV Total Thickness Variation
Warp A measure of flatness, warp being wafers with both convex and concave areas on the surface.
WHT Wafer Heat Treat: a method of cleaning wafers that haven't been through BSD.
WSA Wafer Surface Analysis. Measures the levels of metals surface contamination on a wafer.
WSB Wet Sand Blast: a method of creating backside damage.

Simgui gains the strength from its US-based parter, More Technologies,the acknowledged specialist in epitaxial technology. Simgui is benefiting from close collaboration with such leading substrate suppliers at home and abroad as Forrotec, Gritek and etc. Combing the effective, stable supply channels and its powerful, flexible processing ablility, Simgui has distinguished itself among its domestic and oversea competitors.
Address: 200 Xinlai Road, Jiading District Shanghai 201815, PRC Tel: +86-21-6952 2599 Fax: +86-21-6952 2221